A Design of Ultra-Low Power Low-Dropout Regulator for DSRC system
Sujin Oh, Yong-Deok Ahn, Sung‐Jin Kim, Kang‐Yoon Lee · 2019 34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) · 2019
In this paper, we describe Ultra-Low Power (ULP) Low-Dropout Regulator (LDO) circuits for SPI module management in DSRC system. So LDO is Always-On domain. Circuit uses a CMOS 18 nm process. Proposed ULP LDO's output voltage and input voltage is 3.3 V and 1.2 V and total current consumption is 66 nA. By using 2-Transistor voltage reference circuit, Error Amplifier.