Application of Convolutional Neural Networks to Regenerate Deterministic Test Patterns for BIST
Tsutomu Inamoto, Yoshinobu Higami · 2019 34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) · 2019
This study displays preliminary results on a simple technique to improve fault coverages in the BIST technology. The technique assumes that a circuit which implements an ANN can be used with the target circuit, and effective test patterns are given beforehand. Such ANN circuit is utilized as a degraded memory which approximately regenerates given test patterns. In computational illustrations, fault coverages of test patterns by the technique are calculated on c7552 of the ISCAS'85 benchmark.