Digital Circuits Resynthesis Approach for FPGAs Based on Logic Cell with Built-In Flip-Flop
Ivan V. Tiunov, Ivan A. Lipatov, Daniil A. Zheleznikov · Problems of advanced micro- and nanoelectronic systems development · 2019
This paper discusses a resythesis approach to reducing the area of the FPGA occupied by designed circuit.The approach uses the FPGA's architectural features to merge the combinational element and the sequential element into one logic cell.Merging leads to reduction in the number of elements and to a decrease in the occupied area, in the number of interconnections and, as a consequence, improvement in traceability and temporal characteristics.The proposed approach is valid for FPGAs based on logical cells with built-in flip-flop.Approbation was carried out on IWLS 2005 benchmark and other circuits.