Square Root Carry Select Adder Using Mttspc D-Latch In 90nm Technology
M. V. G. Vara Prasad · i-manager’s Journal on Electronics Engineering · 2019
Carry select look ahead adder is one of the prominent adders used in data path design today. In (Chang & Hsiao, 1998), researchers have designed a carry select adder using carry ripple adder require 29.2% transistors with speed penalty of 5.9% for bit length of 64 bit. The proposed model achieves 6.3% area saving with same speed. Leblebici (1996) has analyzed and designed the CMOS digital integrated circuits. He, Chang, and Gu (2005) have proposed the design for 64 bit square root carry select adder improves the performance with 44% fewer transistors than the conventional one. Kim and Kim (2001) have implemented low power carry select adder using single ripple carry adder. The proposed structure improves the performance with lesser transistor than the dual ripple carry adder. Ramkumar and Kittur (2011) have designed the carry select adder with low power and area efficient. The proposed structure with CSLA is better than the regular square root carry select ahead adder. Pandey, Bakshi, and Sharma (2013) have simulated and synthesized carry select adder for 128 bit with low power and area efficient. The result reveals that the proposed structure reduces area and leakage power with no delay.