Tile Buffer Design for Linear-U Data Layout in Embedded GPU
Jiayun Li, Huimin Du · 2019
Aiming at solving the problem that cache frequent conflict misses in linear layout write back of embedded GPU tile buffer caused by the large address spans, a tile buffer supporting multi-level U-layout is designd, which makes the address continuous when the pixel data is written back where the image resolution is square, reduces the cache conflict misses and improves the cache hit rate. Based on the multi-level U-shaped layout tile buffer, a linear-U-shaped tile buffer supporting rectangular images is proposed, which improves the practicability of the design. Compared with linear layout and multi-level U-shaped layout, the linear-U-shaped tile buffer reduces the circuit area without reducing the cache hit rate. The experimental results show that when configuring tile buffers of different sizes, the multi-level U-shaped layout and the linear-U-shaped layout increase the hit rate by 6.3%-18.5% compared to the linear-layout tile buffer. Compared linear layout and multi-level U-shaped layout, the area of the linear-U-shaped layout circuit is reduced by 15.3% without reducing the cache hit rate.