A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition
Raghavan Kumar, Vikram Suresh, Monodeep Kar, Sudhir K. Satpathy, Mark A Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory Chen, Ram Kumar Krishnamurthy, Vivek K. De, Sanu K. Mathew · 2019
A.A 4900μm2side-channel attack (SCA) resistant AES accelerator in 14nm CMOS achieves 1200x higher minimumtime-to-disclosure (MTD) than an unprotected AES. Randomized byte-order shuffling using heterogeneous Sboxes, linear masked MixColumns and dual-rail key addition enable 9.2x lower correlation between current traces and HD/HW power models. The accelerator achieves 839Mbps throughput with 0.7% performance overhead.