Inspection of Partial Bitstreams for FPGAs Using Artificial Neural Networks
Jens Rettkowski, Safdar Mahmood, Arij Shallufa, Michael Hübner, Diana Göhringer · 2019
Incorporating FPGAs in embedded designs, both for research and industry related applications, is getting increasingly common. Due to the inherent capability of an FPGA to reconfigure itself during run-time, entirely or partially, it has become a very cost effective and time efficient solution for end-users with ever-changing needs for their embedded and custom hardware designs. This capability allowing dynamic reconfiguration of FPGAs, unfortunately also poses a threat to hardware security in terms of malicious bitstream manipulation that can include attacks through intended hardware changes by insertion of hardware trojans, spy-wares or even energy thirsty hardware modules which eventually have adverse effects on energy critical applications. In this paper, we introduce a novel approach to tackle this problem using machine learning techniques for FPGA bitstream analysis. By making use of different Neural Networks, we present how it paves a way to analyze partial FPGA bistreams to trace a certain module, or to find inconsistencies which can be malicious to the target hardware. In contrast to traditional methods to inspect bitstreams, our method saves a significant amount of time.