A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array
Sudhir K. Satpathy, Vikram Suresh, Raghavan Kumar, Vinodh Gopal, James Guilford, Mark A Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Kumar Krishnamurthy, Vivek K. De, Sanu K. Mathew · 2019
A 33,464μm2GZIP decompression accelerator is fabricated in 14nm CMOS, achieving industry-leading 20.5Gbps throughput. The design features out-of-order speculative Huffman decoder to break the fundamental serial dependency resulting in 69% higher decode throughput. The hybrid dual-path decoder provides 2.3× higher performance with multi-write enabled register-file array increasing decompression throughput by up to 41%. The arithmetic-architecture-circuit co-optimized design operates at 1.4GHz at 750mV, 25°C with peak measured energy-efficiency of 1.86pJ/code at 280mV, 2.7× higher than previously reported implementations.