10 Gbps TCP/IP streams from the FPGA for the CMS DAQ eventbuilder network
Gerry P. Bauer, Tomasz Bawej, U. Behrens, James G. Branson, Olivier Chaze, S. Cittolin, J. A. Coarasa, Georgiana-Lavinia Darlea, Christian Deldicque, Marc Dobson, Anne‐Sylvie Dupont, S. Erhan, D. Gigi, Frank Glege, G. Gomez Ceballos, Robert Gómez-Reino, C. Hartl, J. Hegeman, A. Holzner, L. Masetti · Desy publication database (The Deutsches Elektronen-Synchrotron) · 2013
For the upgrade of the DAQ of the CMS experiment in 2013/2014 an interface between the custom detector Front End Drivers (FEDs) and the new DAQ eventbuilder network has to be designed. For a loss-less data collection from more then 600 FEDs a new FPGA based card implementing the TCP/IP protocol suite over 10Gbps Ethernet has been developed. We present the hardware challenges and protocol modifications made to TCP in order to simplify its FPGA implementation together with a set of performance measurements which were carried out with the current prototype.