Performance Comparison of Multi-level Coding Schemes for NAND Flash Memory
Jieun Oh, Seokju Han · IEIE Transactions on Smart Processing and Computing · 2018
Emerging three-dimensional (3D) NAND flash memory devices support new input/output (I/O) modes in which devices can program/read multiple pages sharing a common word line at the same operating time. The new I/O modes enable error-control systems to apply non-binary coding techniques, which are known to achieve capacity-approaching performance in a high signal-to-noise ratio (SNR) regime in conjunction with high-order modulations for NAND storage devices. This paper compares the performance of a number of multi-level-coding/multistage-decoding (MLC/MSD) schemes for NAND flash memory applications. By applying MLC/MSD techniques, it is possible to minimize the code rate loss caused by using the same code designed for the bit level of a page with the highest error rate equal to the remaining bit level of the pages. One considered scheme is an MLC/MSD method applied to 1D and 2D constellations with Bose-Chaudhuri-Hocquenghem (BCH) component codes. Another scheme compared is a special trellis-coded modulation (TCM) method with extra-strong error correction applied to subset labeling bits via Reed-Solomon (RS) code concatenation. In this paper, a new performance analysis method based on semi-analytical block-multinomial modeling is proposed to provide a simpler way to handle correlated error in TCM output. The analytical error rate results and semi-analytical error rate results based on the block multinomial model with the TCM scheme all indicate significant performance advantages from MLC/MSD schemes relative to the baseline BCH coding method.