ISA mapper
Matthew Sotoudeh, Anand Venkat, Michael T. Anderson, Evangelos Georganas, Alexander Heinecke, Jason Knight · 2019
Domain specific accelerators present new challenges for code generation onto novel instruction sets, communication fabrics, and memory architectures. We introduce a shared intermediate representation to describe both deep learning programs and hardware capabilities, then formulate and apply instruction mapping to determine how a computation can be performed on a hardware system. Our scheduler chooses a specific mapping and determines data movement and computation order.