The study of trace cache memory on superscalar DLX processor
Hongwitayakorn Apisake · Adelaide Research & Scholarship (AR&S) (University of Adelaide) · 2003
Background2.1 Overview 2.2 Trace Cache Architecture 2.2.1 The trace cache 2.3 Related Works 2.3.1 The trace cache history v vrr vul xl 2.2.2The fill unit 2.2.3The branch predictor 2.2.4The instruction cache 1 1 2 3 4 4 5 5 7 8 8 8 9 9 9 t4 t6 2.3.2Other high bandwidth fetch mechanism 2.4 Conclusion