Performance Evaluation of Tsunami Simulation Exploiting Temporal Parallelism on FPGAs using OpenCL
Fumiya Kono, Naohito Nakasato · 2019
We developed and evaluated tsunami simulations on FPGAs by designing optimized OpenCL kernels that execute 2-D stencil calculation. By using Intel FPGA SDK for OpenCL, we obtained efficient FPGA designs exploiting temporal parallelism. The performance of our optimal implementation is 446 and 790 GFlops for Arria10 and Stratix10, respectively. These implementations are much faster than a design only exploiting spatial parallelism. The performance on Stratix10 is faster than our GPU implementation on Tesla V100 GPU.