A Layer-Adaptable Cache Hierarchy by a Multiple-layer Bypass Mechanism
Ryusuke Egawa, Ryoma Saito, Masayuki J. Sato, Hiroaki Kobayashi · 2019
The cache hierarchy consists of several cache layers to hide the memory access latency in modern microprocessors, and the capacity and energy consumption of the cache hierarchy increase significantly as the number of layers and their sizes increase. However, since one cache configuration cannot fit all applications, the recent deep cache hierarchy sometimes degrades the energy efficiency of the computing system. In this paper, we propose a layer-adaptable cache hierarchy, which changes the structure of the cache hierarchy according to the memory access behavior of applications by a multiple-layer bypass mechanism. The proposal judges how each cache layer contributes to performance improvement and bypasses ineffective cache layers. Then the data arrays of the bypassed layers are disabled by controlling power supply. The evaluation results show that the proposed mechanism improves the energy efficiency of the computing system by up to 37% and 25% on average while keeping performance.