Area-efficient Radix-32 FFT Processor for Hand Gesture Recognition Radar
Yongchul Jung, Jaechan Cho, Seongjoo Lee, Yunho Jung · JSTS Journal of Semiconductor Technology and Science · 2019
We propose an area-efficient fast Fourier transform (FFT) processor for hand gesture recognition (HGR) radar and present its hardware design and implementation results. To estimate finger motion, the FFT processor should support at least 600~720-point operation for three-channel input data streams. Hence, we propose three-channel 729-point FFT processor based on the radix-3SUP2 /SUPalgorithm and a multipath delay commutator (MDC) pipeline architecture, which minimizes the number of nontrivial multiplications. Moreover, the FFT processor was designed using hardware description language (HDL) and synthesized to gate-level circuits using a standard cell library for 65 nm CMOS process. The proposed architecture results in a logic gate count of 219 K with die size of 0.81mm2 and required memory of 18 KB, which can be suitable for compact HGR radar, as it has a smaller area than similar processors.