Matlab JTAG AXI Master opens new dimensions for development and testability
Mark Fosberry, Ben McMahon · 2019
Mathworks has developed a CPU surrogate interface for FPGAs using the common AXI bus as used by Xilinx and Altera. This FPGA IP block is instantiated as an optional control port into users base design. The IP block only requires JTAG and a system clock to provide full system test access.