Reconfigurable RISC-V Secure Processor And SoC Integration
Zhenya Zang, Yao Liu, Ray C. C. Cheung · 2019
In IoT (Internet of Things) applications, security issues are increasingly attracting attention. However, current embedded processors lack cryptographic protection mechanism. In this paper, an austere RISC-V core processor with RV32I subset instruction is deemed as a master device to cooperate with an AES cryptographic engine in an SoC, due to its openness and flexibility. This core contains separate instructions and a data bus connected to a Wishbone crossbar. A Spartan-6 XC6SLX9 board is taken as an architecture protocol verification platform, where the peak operating frequency of the RISC-V core and the encryption SoC is 105MHz and 111.5MHz, respectively. The hardware resource utilization is reduced compared with the MIPS core with identical efforts