Advanced Regression Management for Post-Silicon Validation of Automotive SOCs
Ayushi Agarwal, Pankaj Gupta, Atul Kumar Gupta · 2018
Gone are the days when an automation framework capable of running a single DUT (Device Under Test) validation regression suite, used to be enough to catch any functionality break in silicon. With the growing complexity of silicon logic and shrinking transistor size (28nm and beyond) such frameworks fail to hit every corner case and defeat the purpose of validation. Latest technology and demanding Automotive market requirements needs next level tools which are capable enough to stress the system and exposes every possible weakness in design. With this mindset, we developed VISTA which is capable of stressing the system where other existing frameworks fail to deliver. VISTA (Validation of Integrated System using Test Automation) is a framework which integrates hardware and software to provide a fully automated test bench for validation. VISTA not only combines various phases of test execution like compilation, execution, capturing of results and logging into server database but also: Automates complex setups involving single and multiple DUTs (Device Under Test), Supports external FPGA for multiple Pin mux validation of low speed interface IPs, Supports OS based performance monitoring (e.g. running Vision/Image processing algorithms on accelerators and Processor Cores in parallel), Provides Voltage-Frequency-Temperature shmoo capability etc. This paper provides a summary of VISTA capabilities and Design principles that helped with a large 28nm Automotive SOC regression management in Post-Silicon validation.