Power and Area Optimized FRA-CSLA for High-Speed NoC Applications
JNTUK, Kakinada, India, Sangeeta Singh · International Journal of Advanced Trends in Computer Science and Engineering · 2019
Network on Chip (NoC) is a well-established research field and is being regarded as an assuring model to solve the complexity of communication barrier in future multicore systems.The major advantage of NoC is on performance and scalability which makes it more suitable to solve problems related to interconnect architecture.The trade-off between area/power consumption and performance is one of the dominant challenges in designing of NoC.To enhance the performance of the design, few of the techniques aim to increase the number or size of the buffers used.But this method in turn leads to increase in area and power consumption.This paper proposes an efficient Flexible Router Architecture-Carry Select Adder (FRA-CSLA) method that occupies less area and consumes less power in comparison to the conventional flexible router design.This method emphasizes on use of CSLA approach to generate next level request signals leading to reduction in area and power compared to conventional method of using basic adder cells.The simulation results depict that this proposed approach improves FPGA and ASIC performance of Flexible Router Architecture (FRA) in comparison to existing method used for NoC.