Architectural tradeoffs with behavioral synthesis
Loganath Ramachandran · 1994
The describe-and-synthesize methodology enables us to exploit current technologies where millions of transistors can be built on a chip. At the behavioral level, the describe-and-synthesize methodology involves the specification of the intended behavior of the design using a hardware description language, and using behavioral synthesis tools to synthesize the RTL structure. The number of architectural alternatives during this synthesis task is large, since it is possible to optimize the design on many different dimensions. In this dissertation, we propose several different strategies for architectural optimizations during the behavioral synthesis process. Specifically, we explore area-optimization techniques, such as component selection from realistic RTL libraries, and clustering of multiple array variables into single memory modules, and performance-optimization techniques such as control pipelining. In order to demonstrate the feasibility of obtaining the architectural tradeoffs with behavioral synthesis, a tool called the Behavioral Design Assistant (BdA) has been developed. A system design methodology that uses such a behavioral synthesis tool can dramatically reduce the design cycle time. This rapid design turnaround time is illustrated using a large industrial example of a fuzzy logic controller.