Hardware Implementation of CORDIC Based Physical Layer Phase Decryption for IEEE 802.11ah
Dai Long Hoang, Thi Hong Tran, Yasuhiko Nakashima · 2019
Being a long range, low power, and low-cost technology, IEEE 802.11ah has gained much attention for developing the Internet of Things (IoT) sensor's wireless transceiver. In general, IoT sensors have a limitation on the power source and computation ability. Therefore, design a low complexity, low power and secure wireless transceiver based on 802.11ah is still challenging. In this research, we develop a low complexity hardware circuit of phase decryption for a variety of high order modulation types of the 802.11ah physical transceiver. We apply Coordinate Rotation Digital Computer (CORDIC) algorithm to calculate the amplitude, phase, sine, and cosine. The designed hardware was synthesized on FPGA and ASIC synthesis. The numerical results have shown that the hardware circuit of amplitude, phase calculation block, and cosine, sine calculation block are low and each block occupies about 10% of the entire decryption. On the contrary, the RC4 stream cipher takes approximately half of the area and power of the entire decryption.