Performance Evaluation of Dynamic Partial Reconfiguration on FPGA by Hardware Time Division Execution
Satoshi Yonemitsu, Akira Yamawaki · 2019
In recent years, the development of mobile terminals such as smartphone is remarkable. However, along with its evolution, there is a problem of increasing the cost and the power consumption by increasing the chip size of system-on-chip (SoC) in terminal. One of approaches tackling this problem is to take advantage of Dynamic Partial Reconfiguration (DPR) on reconfigurable devices. In DPR, large-scale circuits can be time-divisionally executed on a small die in SoC. In other words, cost reduction and power saving can be achieved with the minimum necessary chip size. In this research, we attempt to show a performance merit of DPR by performing a time division execution of a large scale circuit on small portion in a reconfigurable device, Field Programmable Gate Array (FPGA). In addition, we try to estimate how much cost can be reduced in the current general FPGA by using DPR.