Reversible Signed Division For Computing Systems
D. Krishnaveni, Murugesan Geetha Priya · Zenodo (CERN European Organization for Nuclear Research) · 2018
Applications of reversible logic gates in the design of complex integrated circuits provide power optimization. This technique finds a great use in low power CMOS design, optical computing, quantum computing and nanotechnology. This paper proposes a reversible signed division circuit that can divide an n-bit signed dividend with an n-bit signed divisor using non-restoration division logic. The proposed design adequately addresses the ‘delay’ there by improving the efficiency of the circuit. An attempt is made to design a reversible signed division circuit. This paper provides a threshold to build more complex arithmetic systems using reversible logic, thus increasing the performance of computing systems.