Design for Testability of Circuits and Systems; An overview
Emad Khalil, Mohamed H. El-Mahlawy, Fawzy Ibrahim, M. Abdel-Azeem · The International Conference on Electrical Engineering/The International Conference on Electrical Engineering · 2006
Integrated circuits (ICs) are reaching complexity that was hard to imagine. ICs incorporatinghundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc.,are in high demand. Obviously, designing such complex circuits poses real challenges toengineers. Certainly, no relief comes from the competitive marketplace, with increasingdemands for a very narrow window of time (time-to-market) in engineering a ready product.Therefore, a systematic and well-structured approach to designing ICs to be testable is a must.With the growth in complexity of very large scale integration (VLSI) circuits, test generationfor circuits is becoming increasingly difficult and time consuming. Even though thecomputing power and resources have multiplied dramatically over last few decades, anincreasing number of memory elements in VLSI circuits require more effective and powerfulsequential test generators. This paper is represented to review concepts and techniques fortesting electronic circuits and systems as part of a lecture review.This covers various testing and design-for-test (DFT) techniques starting from (AutomaticTest Equipment) ATE basics (definition, construction and types). Exploring testing strategiesfor digital combinational and sequential circuits, and introduces a comparative study betweenthe common fault models. Finally the paper ends with design for testability guiding rules andpossible challenges and difficulties that need development and research in the testingproblem.