Design and Implementation of Parallel Branches for Concatenated BCH and LDPC Coding on FPGA
Ahmed Mahdy, Mohamed Helmy, Mohamed A. S. Hassan · 2019
Recently, satellite services applications are of wide utilization as in radio and television broadcast, voice and data communication, and location services communication. Error correction codes are continuously designed to accomplish reliable communication with low Bit-Error-Rate (BER) in satellite communication link. Modern techniques are using concatenation of different codes, to achieve low BER. This paper presents an implementation for Bose-Chaudauri Hocquenghem (BCH) on FPGA. Also, it provides an implementation for low density parity check (LDPC) on FPGA. Finally, a design and implementation for multiple branches of BCH concatenated with LDPC on FPGA, where the encoder is designed such that two parallel BCH branches are concatenated with one LDPC, while the decoder design is four parallel BCH branches concatenated with one LDPC. This proposed design improves the link reliability and increases the throughput when compared with the serial concatenated coding systems, where the encoder throughput increased from 100 Mbps to 200 Mbps, and the decoder enhanced from 10.5 Mbps to 50 Mbps.