NEW AUTOMATIC TESTING ARCHITECTURE FOR INTEGRATED CIRCUITS
Sherif Anas, Mohamed H. El-Mahlawy, Ehab. Elsehely, Al-Emam Ragab · The International Conference on Electrical Engineering/The International Conference on Electrical Engineering · 2006
In this paper, a complete example for BIST (Built-In Self-Test) boundary scan architectureand 16-bit multiplier as the CUT is presented. Adding BIST boundary scan capabilities to thedigital VLSI integrated circuit design makes the electronic card testable from five pins TMS,TCK, TDI, TDO and TRST* that is optional. The simulation and then design download arepresented on the Spartan Xilinx X2C100 chip. The hardware implementation is tested usingthe interfacing through the parallel port of the personal computer that supplies required fivecontrol pins. This approach will lead to the concept of the portable ATE (Automatic TestEquipment). All required test circuitry is embedded in the integrated circuits and the controlof the test circuitry is supplied from the TAP (Test Access Port) controller. Finally, the TAPcontroller is controlled from the parallel port of the personal computer. So, the personalcomputer is used as a master controller and the TAP controller is used as a slave controller.The presented idea of the new BIST testing architecture solves the testing problem of thedigital VLSI circuits using the traditional ATE.