Energy efficient VLSI architecture of real‐valued serial pipelined FFT
Jinti Hazarika, Mohd. Tasleem Khan, Shaik Rafi Ahamed, Harshal Bhalchandra Nemade · IET Computers & Digital Techniques · 2019
This study presents an energy‐efficient serial pipelined architecture of fast Fourier transform (FFT) to process real‐valued signals. A new data mapping scheme is presented to obtain a normal order input–output without the requirement of a post‐processing stage. It facilitates reduction in the computational workload on the hardware resources which is confirmed through mathematical derivations. Further, the proposed design involves a novel quadrant multiplier with relatively lower hardware complexity. It performs the quarter operation of a complex multiplier in one clock cycle, and thereby consumes relatively lower power. Moreover, in the last stage, a merged unit for butterfly computation and data re‐ordering is also proposed which performs either a half‐butterfly operation or interchanges data, and thereby reduces the hardware usage. Application specific integrated circuit synthesis and field programmable gate array results show that for a 1024‐points FFT computation, the proposed architecture offers 10.26% savings in area, 20.83% savings in power, 16.98% savings in area‐delay product and 26.76% savings in energy‐per‐sample, 7.79% savings in sliced look‐up tables, and 11.93% savings in flip‐flops over the best existing design.