Sonar: Writing Testbenches through Python
Varun Sharma, Naif Tarafdar, Paul Chow · 2019
Design verification is an important though time-consumingaspect of hardware design. A good testbench should supportperforming functional coverage of a design by making it easy to implement tests and determine which tests are being performed. However, for complex designs, creating and main-taining effective testbenches can take increasing amounts of time away from actual design. A further complication is there may be two development flows: conventional hardware written in a hardware description language (HDL) such as Verilog orVHDL and high-level synthesis (HLS). In the HLS approach, the hardware is specified in a higher-level language (HLL) and then converted to an HDL through HLS tools. In this flow, testbenches for the design are written in the same HLLand cosimulation is used to verify the generated HDL. Due totool restrictions, cosimulation may not always work. In VivadoHLS [1] for example, the design must contain control signals to define when to start and stop the module or the initiation interval for new data must be one cycle. Without cosimulation, the user must write an HDL testbench manually in addition to a testbench in the HLL for preliminary verification. To simplify writing testbenches, we present Sonar: an open-source Python library to write cross-language testbenches. From a common source script, Sonar can generate testbenches written in SystemVerilog (SV) and C++. These files can then be imported into standard simulation tools such as ModelSim[2] or Vivado HLS and run. The use of Python makes it easy to extend Sonar with higher layers of abstraction for testbenches and integrate it with other software platforms.Sonar is available at https://github.com/UofT-HPRC/sonar.