Highly Efficient GF(2 8 ) Inversion Circuit Based on Redundant GF Arithmetic and Its Application to AES Design.
Rei Ueno, Naofumi Homma, Yukihiro Sugawara, Yasuyuki Nogami, Takafumi Aoki · 2015
Abstract. This paper proposes a compact and efficient GF (28) inver-sion circuit design based on a combination of non-redundant and redun-dant Galois Field (GF) arithmetic. The proposed design utilizes redun-dant GF representations, called Polynomial Ring Representation (PRR) and Redundantly Represented Basis (RRB), to implement GF (28) in-version using a tower field GF ((24)2). In addition to the redundant rep-resentations, we introduce a specific normal basis that makes it pos-sible to map the former components for the 16th and 17th powers of input onto logic gates in an efficient manner. The latter components for GF (24) inversion and GF (24) multiplication are then implemented by PRR and RRB, respectively. The flexibility of the redundant rep-resentations provides efficient mappings from/to the GF (28). This pa-per also evaluates the efficacy of the proposed circuit by means of gate counts and logic synthesis with a 65 nm CMOS standard cell library and comparisons with conventional circuits, including those with tower fields GF (((22)2)2). Consequently, we show that the proposed circuit achieves approximately 40 % higher efficiency in terms of area-time product than the conventional best GF (((22)2)2) circuit excluding isomorphic map-pings. We also demonstrate that the proposed circuit achieves the best efficiency (i.e., area-time product) for an AES encryption S-Box circuit including isomorphic mappings.