20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
2005
The following are topics are dealt with: yield analysis and modeling; scan design and test data compression; reconfiguration; error correcting codes and circuits; fault detection; fault tolerance; sensors; flash memories; error tolerance; delay fault test and timing consideration; QCA circuits; interconnect test; soft errors; test scheduling; software-based test; analog circuit design and testing.