Implementation of a Pipeline-Based BCH Decoder Architecture to Reduce the Delay and Hardware Complexity
Masoud Hazrati, Javad Javidan, Shahram Jamali · 2017
With the rapid development of information technology in various fields as well as need for high-speed storage and retrieval of information, It provides a bed to produce the high-speed memory and are also less hardware complexity. As a result, storage speed and hardware complexity as a major challenge in the memory structure has become. To meet this challenge in memory controller, the embedded Error Correction Codes (ECC) block called the main task is to overcome the high rate of error, as to increase the speed and reduce the complexity of hardware error correction codes are used. Error correction codes are used in a variety of studies that have been done in NAND Flash memory controller. Bose-Chaudhuri-Hocqunghem (BCH) error correction codes in this thesis structure and BCH encoder and decoder examined two blocks, and ways to optimize the BCH decoder blocks to be offered to enhance the efficiency of data storage. The BCH codeword is decoded by passing through three stages: calculating the syndrome, calculating the error location polynomial and the Chien search algorithm to find error locations. There are two challenges in the optimization process of BCH decoder: speeding up the computation and reducing the hardware complexity. The delay in the process of error correction and hardware size of each sub-blocks. To increase efficiency, the BCH decoder architecture has been proposed pipeline. The proposed solution for reducing hardware complexity and increase the speed of our other decoder block BCH, using an algorithm based on factoring in Chien Search block that has the most hardware complexity is BCH decoder block. Hardware description language VHDL simulation methods proposed by then to assess the parameters of time, frequency, power and operation of hardware in the Quartus II synthesis. The proposed method is applied on the set of data and process time while maintaining the original function has been able to block decoder BCH error correction and reduce hardware complexity and increases the efficiency of the BCH decoder.