Design of 32 bit Asynchronous RISC CPU Using Micropipeline
Pranjal Srivastva, Pritesh Kumar Yadav, Prasanna Kumar Misra · 2018
In this work, the 5-stage pipeline 32-bit Asynchronous RISC CPU has been designed. The asynchronous CPU was synthesized using the standard cells of SCL 180 nm CMOS technology. The performance parameters were obtained through simulation. The interconnect power, area and delay were estimated by comparing the simulation results of pre-layout and post-layout of the design. The results were compared with the synchronous CPU. The power calculated for the asynchronous RISC CPU is 117 mw which is 69 % less than synchronous CPU. Further, the effective switching capacitance of asynchronous CPU is reduced by 69 % compared to the synchronous CPU. The figure of merit shows that asynchronous CPU can be used for low power IoT chip.