Optimized FPGA Implementation of the CRC Using Parallel Pipelining Architecture
Noor Najeeb Qaqos · 2019
Cyclic Redundancy Check (CRC) plays a major role in data storage, communication systems and networking environment fields to detect errors. The speed of transmitting data with optimized hardware utilization are the main challenges nowadays. Thus, CRC calculation becomes a bottleneck for the system implementations. The aim of this paper is to design and implement the CRC5 and CRC8 systems that are used for USB token packet and ATM protocols, respectively. A parallel pipelining method is used to implement the proposed CRC architecture for both CRC encoder and decoder systems to achieve high throughput data with optimized hardware resources. A proposed architecture doesn't base on Look-Up Table (LUT) to store pre-calculated CRC values or F-matrix in its implementation as in the previous works. The system designed and implemented based on Spartan-3E FPGA chip, Very High-Speed Integrated Circuit Description Language (VHDL) used to write the related code. The whole proposed architecture is functionally simulated and verified using the Xilinx ISE 9.2i simulator.