Efficient parallel semi-systolic array structure for multiplication and squaring in GF(2m)
Atef Ibrahim, Usman Tariq, Tariq Ahmad, Ahmed Elmogy, Yassine Bouteraa, Fayez Gebali · IEICE Electronics Express · 2019
In this paper, we develop an efficient parallel semi-systolic array structure to concurrently compute multiplication and squaring operations in the binary extension field, GF(2m), for efficient modular exponentiations. The proposed array is well suited to VLSI implementation that it has a regular structure as well as local communications between its processing elements. The obtained results show that the proposed array structure achieves a significant reduction in area-time (AT) complexity by at least 95.9% over the corresponding existing structures.