RTL Test Generation on Multi-core and Many-Core Architectures
Aravind Krishnan Varadarajan, Michael S. Hsiao · 2019
Design Verification of complex circuits has become an increasingly time-consuming process. The advent of parallel computing using General Purpose Graphics Processing Units (GPGPUs) has led to enhanced performance for various applications. We propose to leverage both the multi-core CPU and the GPGPU for RTL test generation. This is achieved by implementing a test generation framework that can utilize the SIMD type parallelism available in GPGPUs and task level parallelism available on CPUs. Not all applications can be made parallel due to complex dependencies, making parallelism non-trivial. Besides, large memory bandwidth requirements can become a bottleneck hindering potential speedups. In this paper, we have ported an RTL branch coverage based test generation framework to work within the constraints of a GPGPU environment. Experimental results show that considerable speedup can be achieved for test generation without loss of coverage.