Fast BCH syndrome generator using parallel polynomial division algorithm for GPGPUs
Arul K. Subbiah, Tokunbo Ogunfunmi · 2019 IEEE 6th International Conference on Industrial Engineering and Applications (ICIEA) · 2019
Recent developments in General Purpose Graphical Processing Units (GPGPU) has attracted many researchers to invent new methods to decode errors for linear block codes such as Bose-Chaudhuri-Hocquenghem (BCH), and Reed Solomon (RS) codes. In this paper, we propose a parallel polynomial division algorithm to compute the syndromes of a received BCH code. Further, using the parallel thread technique offered by the GPGPUs, we propose to use the same to generate the parity bits of the BCH encoder. We have devised an engine to compute the syndromes for BCH codes with field extension m=15, and we studied the GPU implementation of the same for bit errors t=2..15. The results, when compared against the conventional syndrome generator, has a minimum of 12% improvement in the efficiency of the syndrome generator kernel routines. Hence, this method provides an efficient way to compute syndromes for a programmable error correction mode.