Automatic Implementation of Secure Silicon
Serge Leef · 2019
Throughout the past decade, cybersecurity threats have evolved from attacks focused high in the software stack to progressively lower levels of computational hierarchy. With the explosion of popularity and growing deployment of internet connected devices, economic attackers and nation-states alike are shifting their attention to Application Specific Integrated Circuits (ASICs) that enable complex capabilities across commercial and military application domains. Despite growing recognition of the problem and a substantial body of research across multiple chip security areas, no common tools, methods or solutions are in wide use today. Modern synchronous digital ASICs are already very complex and expensive to design and incorporation of security is viewed as a burden with unclear economic benefits. The result is that the majority of today's ASICs are largely unprotected. Absence of automation makes incorporation of security a laborious, manual task that generally requires very specific design expertise not generally possessed by semiconductor companies. These dynamics can be altered with a novel chip design flow that aims to protect advanced ASICs from known attack strategies by streamlining inclusion of scalable defense mechanisms into an automated process that maximizes architectural exploration of security vs. economics trade-offs while improving design productivity. The effort and cost to incorporate a level of hardware security aligned with application requirements and economics will be significantly reduced so that incorporation of security at all levels of hardware design is feasible and affordable.