Write Variation Aware Non-volatile Buffers for On-Chip Interconnects
Khushboo Rani, Hemangee K. Kapoor · 2019
With the advancement in CMOS technology and multiple processors on the chip, communication across these cores is managed by a Network on Chip (NoC). Power and performance of these NoC interconnect have become a significant factor. In particular, the buffers used at every port consume considerable dynamic as well as leakage power. This paper attempts to reduce leakage power consumption of NoC buffers by use of non-volatile memory (NVM) technology based STT-RAM buffers. STT-RAM technology has the advantage of high density and low leakage but suffers from high write energy and low endurance. In particular, if some buffers get written more number of times compared to some other buffers, the heavily written buffers may wear out faster compared to others. This has an impact on the lifetime of the router as a whole. Here we propose a virtual channel (VC) allocation policy that helps to uniformly distribute the writes across the buffers to improve their effective lifetime. Pure STT-RAM buffers, however, impact the network latency. In order to mitigate this, we propose a hybrid policy that uses an alternative VC made of SRAM technology in case of heavy network traffic. Experimental evaluation on full system simulation shows that the proposed policy reduces the write variation by 99% and improves lifetime by 3.4 times and 24 times, respectively for both the proposals. We also get respectively 93% and 90% gains in the EDP.