Achieving Performance Speed-Up in FPGA Based FIR Filters Using DSP Macro Blocks
Burhan Khurshid, Mayidah Manzoor, Kurteeba Muzaffar, Bazilla Wani, Basit Mushtaq · 2019
Processor based implementation of DSP algorithms often result in poor performance as the architecture is being sacrificed to achieve the ease in programmability. This has prompted designers to use different hardware platforms, where in the architecture can be specifically developed to achieve the requisite performance. Very recently FPGAs have featured as a viable platform for realization of different DSP algorithms. However, owing to increased performance requirements, the traditional LUT based FPGAs fail to achieve the desired results. This has prompted vendors to improve the quality and quantity of the underlying FPGA fabric. One such improvement has been the inclusion of special DSP macro blocks in modern FPGAs. These assist in fast and optimal realization of different arithmetic operations like addition, multiplication etc. In this paper, we consider the realization of Direct and Transposed FIR filter structures using these DSP blocks. Detailed experimentation using Xilinx Spartan-6 FPGAs shows a subsequent improvement in performance when compared to traditional realizations.