Seamless SoC Verification Using Virtual Platforms: An Industrial Case Study
Kyungsu Kang, Sang‐Ho Park, Byeongwook Bae, Jungyun Choi, SungGil Lee, Byunghoon Lee, Jong-Bae Lee · 2019
As SoC (System-on-Chip) complexity continues to increase, function/performance verification is required in the middle of design process (before tape-out) to reduce the possible risks ranging from over-design to non-compliance with the design specifications. In this paper, we propose a seamless SoC verification. The proposed methodology exploits a modern virtual platform (VP) technology which can combine high-level C++ firmware, timing-accurate SystemC models, and RTL (register-transfer level) designs. Thus, the full-chip level verification can be done at any design stages in the whole development process. With experimental results, this paper shows the benefits and lessons of using VPs.