A Fine-grained Integrated IP Lookup Engine for Multigigabit IP Processing
Sanchita Saha Ray, Sonal Singh, Chandrayan Sengupta, Surajeet Ghosh, Bhaskar Sardar · 2018
This paper proposes a fine-grained hardware for integrated look-up architecture to process IPv4 and IPv6 packets. A TCAM-based LPM search architecture is designed to accommodate IPv6 addressing scheme along with the existing IPv4 addressing scheme in an efficient and integrated manner. The architecture is able to deal with immense IP traffic growth and network speed to support multi-gigabit/sec bit rate using lower memory requirement. Moreover, This engine does not require any sort of prefix ordering according to their prefix length unlike conventional TCAM based schemes. Furthermore, it provides an efficient and fast LPM structure by involving only some digital logic gates those operate in a systematic fashion with/without parallel working mechanism. The numerical results show that this lookup engine remarkably decreases memory requirement. The time needed to search a prefix and to perform next-hop lookup is ≈ 1 clock cycle each. The proposed engine performs an LPM lookup in 3.17 ns (IPv4) and 3.12 ns (IPv6). The average search throughput exhibited by the proposed engine is beyond OC-768 wire-speed and is roughly 70 Gbps.