BCH Decoder Design to Improve Memory Reliability and Error Correcting in Flash Memories
Saeideh Nabipour, Javad Javidan, Gholamreza Zare Fatin, Mehdi Nooshyar · 2015
Reliability of NAND Flash cells has become an increasing concern, especially with reducing in geometry of semiconductor cell and transistor size. Error Correction Codes (ECC) are used in NAND Flash memory to overcome this challenge which its main task isto overcome thehigherrorrates. Recently, there has been growing research onerrorcorrecting codesusedinNAND Flashmemorycontroller. One of the most common error correction codes in commercial NAND Flash memory is Bose-Chaudhuri-Hocqunghem (BCH) codes. TheBCHerror correctioncodes is implemented through two blocks: 1) BCH encoder 2) BCH decoder, which weintroduced themthen we have used a new optimized method that not only maintains the reliability of cell but also improves the memory efficiency. The BCH codeword is decoded by passing through three stages: calculating the syndrome, calculating the error location polynomial and the Chien search algorithm to find error locations. Thereare twochallengesinthe optimization process ofBCHdecoder: speeding up the computationand reducingthe hardware complexity. To increase the decoding throughput, a parallel decoder is used by utilizing parallel architectures for various building blocks. To implement parallel BCH decoder in an area-efficient manner, an iterative matching scheme is proposed to reduce the Chien search hardware complexity. The proposed scheme reduces common modulo 2 additions within groups of Galois Field (GF) multiplier in Chien search block. The encoder and decoder blocks have been implemented by VHDL language programming and synthesized in Xilinx ISE. The proposed method applied on set of codewords and could reduce the decoding time and hardware complexity