Refresh optimised embedded-dram caches based on zero data detection
Sheel Sindhu Manohar, Hemangee K. Kapoor · 2019
Muti-level cache hierarchy with large sized last level caches (LLCs) have emerged to minimise the performance gap between the processing cores and the main memory. Traditionally, LLCs are made using SRAM technology, however, recent trends have shown that dense and low leakage consuming embedded-DRAMs (eDRAM) are a good alternative to SRAM. The only challenge for this replacement is the time and energy consumed by the periodic refresh demanded by eDRAMs.