Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory
Junyoung Ko, Younghwi Yang, Jisu Kim, Cheonan Lee, Young-Sun Min, Jinyoung Chun, Moo‐Sung Kim, Seong‐Ook Jung · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2019
Research on a word-line (WL) driving scheme is essential because the effect of WL parasitic resistance and capacitance (RC) is more severe for high-capacity NAND flash memories. The WL under-driving scheme (WLUDS) mitigates the effect of parasitic RC by reducing the coupling capacitance between WLs. However, WLUDS increases the cell threshold voltage (Vth) distribution because of parasitic RC variation, which causes an overshoot of the programming voltage (VPGM). In this study, we propose the variation-tolerant WL under-driving scheme (VTWLUDS) to reduce the effect of parasitic RC variation and VPGMovershoot through the use of a three-phase VPGMcontrol. We also introduce the fast-verify WL driving scheme (FVWLDS) to reduce the effect of parasitic RC variation in the verify operation. We verified VTWLUDS and FVWLDS by performing an HSPICE simulation with Samsung's transistor model for a NAND peripheral circuit. The simulation results showed that VTWLUDS achieved a sufficient Vthshift during the programming operation regardless of the WL parasitic RC variation. By using VTWLUDS and FVWLDS, we achieved 1304 μs of total programming time (TPROG) for a 512-Gb planar-type NAND flash memory.