Towards Analysing the Effect of Snoozy Caches on the Temperature of Tiled Chip Multi-Processors
Ashwini A. Kulkarni, Chirag Joshi, Khushboo Rani, Sukarn Agarwal, Shrinivas Padmakar Mahajan, Hemangee K. Kapoor · 2018
Advancement in semiconductor technology has packed more and more transistors on the chip leading to more processing power. This processing power comes at the cost of heavy energy consumption and heat dissipation. This increase in chip temperatures needs to be controlled as it adds to the cooling costs and may also damage the on-chip circuitry if not kept under a limit. Large on-chip caches though considered as cooler components still exhibit 30°C spatial variance in temperature. A major contributor to this temperature is the leakage current. To control the leakage current we can either turn-off the components or run them at low voltage mode. In this paper, we run certain cache banks at low voltage mode in order to control the leakage. We demonstrate that the low power states can also assist in controlling the temperature of the cache as well as its nearby components. However, low voltage cache blocks need extra time for accessing as they need to be boosted up for every read. This might hamper the performance. To control the performance degradation, in this work we choose to lower the voltage of cache banks that have the least usage. Experimental evaluation shows 2.7° reduction in average chip temperature with a negligible effect on performance.