ReDC: Reduced Deflection CHIPPER Router for Bufferless NoCs
Rose George Kunthara, Rekha K. James, Simi Zerine Sleeba, John Jose · 2018
Network on Chip (NoC) is emerging as a promising design paradigm as an on-chip interconnect for multi-core architectures to overcome scalability and bottleneck issues of traditional bus-based and point-to-point communication architectures. Minimum packet latency, power and area with improved performance are the important characteristics that determine the efficiency of an NoC router. In this paper, we propose a bufferless deflection router, ReDC, which minimizes the deflection rate of flits by selecting a Permutation Deflection Network with an input combination that gives most number of productive output ports. Simulation results indicate that our proposed design improves network saturation point, reduces deflection rate and average flit latency without significant change in critical path delay when compared to contemporary bufferless deflection routers.