Implementation of a Fuel Estimation Algorithm on SoC FPGA
Imed Ben Dhaou, Faisal Omar Mahroogi, Hannu Tenhunen · 2019
This paper proposes hardware architecture for a fuel estimation algorithm suitable for SoC FPGA. The architecture utilizes 32-point single precision floating point representation. A resource constraint scheduling algorithm is elaborated to synthesize an area efficient architecture. The floating point arithmetic is implemented using commercial IP. Synthesis results for the Virtex-6 FPGA family reveal that the proposed architecture consumes 1655 slices, has a latency of 71 ns and consumes 0.15 µJ. Additionally, the present work describes a software implementation of the fuel estimation algorithm using Zynq-7000 SoC.