Non-blocking Gated Buffers for Energy Efficient on-chip Interconnects in the era of Dark Silicon
Khushboo Rani, Sukarn Agarwal, Hemangee K. Kapoor · 2018
The era of dark silicon demands that several components on the chip (i.e. cores, memory and NoC) need to be powered-off or run in low-power mode. This is mainly due to the increased leakage power consumption at smaller technology nodes. Even when core components are turned-off the communication network is expected to maintain connectivity. Therefore the challenge shifts to designing NoC with low power consumption with a reasonable throughput. NoC router power consumption can be controlled by powering-off the router when idle and waking it when traffic arrives. However, in such approaches, the wake-up cycles add to the packet latency affecting the performance. It has been observed that buffers in a router are the main contributors to leakage. In this paper, we attempt to reduce leakage power of network-on-chip by keeping the routers powered on, but keeping most of the buffers in the powered-off state. In the context of dark silicon, for the routers attached to the gated cores, we keep most of the buffers powered-off saving their leakage energy. In order to maintain connectivity, we keep a minimal number of buffers powered-on that help in traffic management without adverse effect on the performance. Experimental evaluation shows significant savings in leakage energy with the marginal performance penalty. Results are shown in comparison to a baseline using no power gating and with another existing policy.