Fault tolerant routing algorithm in networks on chip using ant colony algorithm
Rahman Ghahremani, Javad Javidan, Shahram Jamali · 2015
: Increasing of design complexity of integrated circuits on one hand and need to segregate activities of computation and communication sections in today's IC chips on the other hand, has directed design path towards systems based on network- on-chip. Nowadays, having high reliability in face of unwanted environmental factors is an important goal in the designing of computational systems; factors against which the vulnerabilities of circuits are ever more increasing as the sizes continually diminish in the areas of chip manufacturing technologies. In this respect, the networks-on-chip, as a scalable communication substructure in systems-on-chip, should possess this characteristic. In this thesis, the networks-on-chip have been examined with respect to their internal structure and various types of connections and breakdowns, and also different routing algorithms and fault-tolerant routing algorithms against permanent faults and problems have been introduced and presented. Then, the designs of two types of routing algorithms tolerant of connection faults, have been presented, that in first method we use ant colony algorithm and how ants can skip the obstacles when searching for food sources. In this method packets was considered as ants and obstacles as a failures. to further explore a second method is proposed. This algorithm is based on DyXY algorithm that tolerance permanent link failures and also the algorithm is aware of the congestion. The simulation results show that the proposed algorithm has better performance in all evaluation parameters such as delay and reliability than planar adapt routing algorithm.