Transistor Count Reduction by Gate Merging
Calebe Micael de Oliveira Conceicao, Ricardo A. L. Reis · IEEE Transactions on Circuits and Systems I Regular Papers · 2019
A large set of ASICs uses much more transistors than its necessity, as they use a library of cells with a limited amount of logic functions. This small number of logic functions in a traditional cell library represents an inherent limitation in the optimization of the number of transistors. In modern technologies, static power consumption is related to the number of transistors. To reduce leakage power, it is necessary to optimize the number of transistors. Therefore, it demands the use of a library-free physical design approach, using tools to allow the automatic layout synthesis of any transistor network. The goal of this paper is to present a new method to optimize the logical netlist, willing to reduce the number of transistors and connections, as well as the number of vias. Post-processing of the original logic netlist generated in a traditional design flow is completed, and a set of basic cells is replaced by just one new equivalent logic gate, thus simultaneously reducing the number of transistors. The connected cells of unitary fanout are considered to be merged into a new complex gate (usually not available in a traditional cell library). This approach is capable to reduce the number of transistors of a circuit by 21% on average when compared to the traditional solution, and by 4% when compared to other logic minimization tools. This provides an important leakage power reduction.